Multiphase clocks are useful in many applications. In high-speed serial link applications, multi-phase clocks are used to process data streams at a bit rate higher than the internal clock frequencies. In clock multiplier applications, multiphase clocks are combined to produce the desired output frequency for the synthesizer. In microprocessors, multiphase clocks can ease the clock constraints in the pre-charge logic to achieve higher operating speeds. In wireless designs, radio frequency multi-phase clocks are required for direct conversion, while in baseband circuitry the multiphase clocks can be used to find a better sampling point for the analog-to-digital converter (ADC) to improve overall system performance.
Several techniques are known in the art for implementing multi-phase clock generation. Some of those techniques are listed below:
1. Multiphase voltage-controlled oscillator (M-VCO) (see, for example, Mazzanti, et al, “Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at Ka-Band,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, iss. 2, pp. 355-363, 2008 (incorporated by reference));
2. Delay Locked Loop (DLL) (see, for example, Craninckx, et al., “A harmonic quadrature LO generator using a 90° delay-locked loop,” in Proc. European Solid-State Circuits Conf. (ESSCIRC), 2004, pp. 127-130 (incorporated by reference));
3. Quadrature through a Frequency Division (see, for example, Bonfanti, et al., “A 15-GHz broad-band/2 frequency divider in 0.13 μm CMOS for quadrature generation,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 11, pp. 724-726, November 2005 (incorporated by reference));
4. Quadrature through Poly Phase Filter (see, for example, Kaukovuori, et al., “Analysis and design of passive polyphase filters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 10, pp. 3023-3037, November 2008 (incorporated by reference); and
5. Injection Locked Ring Oscillator (see, for example, Grozing, et al., “CMOS Ring Oscillator with Quadrature Outputs and 100 MHz to 3.5 GHz Tuning Range,” Proc. 29th European Solid-State Circuits Conf. (ESSCIRC 03), IEEE Press, 2003, pp. 679-682 (incorporated by reference)).
Each of these techniques presents one or more disadvantages for a wide-band application.
The M-VCO technique uses four stages connected as shown in the example of FIG. 1. The signal produced from the in-phase side of the oscillator is injected in the quadrature-phase side of the oscillator, and vice versa. The inversion present in the ring feedback allows for the generation of two signals in quadrature. There are two known implementations through use of an LC-tank circuit or a delay cell.
The LC-tank VCO implementation ensures an adequate spectral purity of the generated clock. This circuit can be tuned to work over a range of frequencies acting on the value of the inductor or the capacitor composing the tank. For high frequency applications, variable capacitors, used as tuning elements in VCOs, present poor quality factors for a given tuning range, and dividers used in the phase-locked loop feedback path are power hungry. LC-tank VCOs have been successfully used in narrowband systems. A trade-off between tuning range and phase noise is present. Moreover, multiphase oscillators show a high phase noise, in particular a flicker component that is up-converted into phase noise.
The delay cell VCO solution employs cells with a variable delay. To achieve oscillation, the ring must provide a phase shift of 2π and have unity voltage gain at the oscillation frequency. Each delay stage must provide a phase shift of π/N, where N is the number of delay stages. This approach is commonly affected by problems related to process variations and mismatches. An additional weakness of this circuit is represented by the jitter accumulated along the loop related to the phase uncertainty, corresponding to a high phase noise compared to what is achieved by LC-tank implementations.
The DLL solution, as in the ring oscillator, exploits the use of delays cells as depicted in FIG. 2. Unlike the ring oscillator, in this case a digital loop is commonly used. A signal at the desired frequency is provided at the input of the chain. A phase detector is used to compare the output and the input phase difference. This information is used to calibrate the delay in each cell to provide equally spaced phase versions of the same input clock. The drawbacks of this solution include: sensitivity process variations and mismatch; accumulation of jitter along the loop and complex calibration logic.
Another solution generates the quadrature signals through the use of a frequency divider. The generation of two clocks in quadrature can be done by the double sampler configuration as shown in FIG. 3. This solution is wide-band by construction. To properly work, this architecture requires at its input a clock at the twice the desired frequency. This signal can be provided by an oscillator that works in a range of frequencies that is the double of the desired frequency. This double-speed requirement heavily impacts the VCO design. Indeed, the divider circuit quickly becomes power hungry as the frequency increases. Another drawback of this solution is that it can only produce two output phases.
The poly phase filter (PPF) solution is shown in FIG. 4. The simplest way of generating the I-Q signals is with an RC-CR network: the signal at the in-phase I-output has a 45-degree phase lag, and the signal at the quadrature-phase Q-output has a 45-degree phase lead. Both signals are attenuated by 3 dB. So, at the pole frequency both phase and amplitude are in balance. This structure offers a constant 90-degree phase shift only at the RC frequency and it suffers from amplitude imbalance. Yet another problem is component mismatch: which results in the two RC products being unequal, and this generates a phase error. Hence, better matching is achieved with a larger die area. Another drawback of this solution is that it can only produce two output phases.
The injection locked ring oscillator technique has a block diagram as shown in FIG. 5. This circuit utilizes a loop made of four delay cells, one of which is injected by an input frequency signal. The output signals show the frequency and the phase noise of the input signal. The main drawback of this approach is that it is commonly affected by problems related to temperature and supply variations.
There is a need for an improved ring oscillator circuit that will generate multiple equally-spaced clock phases starting from a unique clock phase signal at the same frequency with high phase accuracy.